Datenprozessor mit Speicher zur Verarbeitung ausgestatteter Befehle mit Cache-Umgehung

Details

Veröffentlichungs-Nr.

EP2431866

Aktenzeichen

EP11177484

Anmeldetag

12. August 2011

Veröffentlichung

14. Oktober 2015

Erteilung

14. Oktober 2015

Rechtsraum

EP

IPC

G06F9/30G06F12/08G06F9/38// G06F15/78

Abstract

A method includes determining if a data processing instruction (300) is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache (43). When the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further includes invalidating a cache entry of the cache associated with the cache hit; and performing by a memory controller (72) of the memory (40), a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location.

Anmelder

Firma

Freescale Semiconductor, Inc.

Land

🇺🇸 USA

Fachgebiete