Zeitlich gemultiplexter Mehrportspeicher

Details

Veröffentlichungs-Nr.

EP2587486

Aktenzeichen

EP12189371

Anmeldetag

22. Oktober 2012

Veröffentlichung

11. September 2019

Erteilung

11. September 2019

Rechtsraum

EP

IPC

G11C7/10

Abstract

Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Anmelder

Firma

Altera Corporation

Land

🇺🇸 USA

Fachgebiete