Anti-Faltungsverzerrungs-Abtastschaltungen und Analog-Digital-Wandler

Details

Veröffentlichungs-Nr.

EP2744112

Aktenzeichen

EP13005868

Anmeldetag

17. Dezember 2013

Veröffentlichung

3. April 2019

Erteilung

3. April 2019

Rechtsraum

EP

IPC

H03M1/12// H03M1/46

Abstract

A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.

Anmelder

Firmen

Linear Technology Corporation
Dust Networks Inc.

Land

🇺🇸 USA

Fachgebiete