PLL-Schaltung
Anmelder: YAMAHA CORPORATION 🇯🇵
Details
- Veröffentlichungs-Nr.
- EP2782254
- Aktenzeichen
- EP14160829
- Anmeldetag
- 20. März 2014
- Veröffentlichung
- 19. August 2015
- Erteilung
- 19. August 2015
- Rechtsraum
- EP
- IPC
- H03L7/14
Abstract
A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector (101) for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device (107) for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.
Anmelder
- Firma
- YAMAHA CORPORATION
- Land
- 🇯🇵 Japan
Japanischer Konzern, der Musikinstrumente, Audio- und Unterhaltungselektronik sowie Halbleiterkomponenten entwickelt und produziert. Das Unternehmen mit Sitz in Hamamatsu wurde 1887 gegründet.
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