Stromsparbetrieb eines Cachespeichers

Details

Veröffentlichungs-Nr.

EP2808758

Aktenzeichen

EP14166906

Anmeldetag

2. Mai 2014

Veröffentlichung

3. November 2021

Erteilung

3. November 2021

Rechtsraum

EP

IPC

G06F1/3206G06F1/3234

Abstract

In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA

Fachgebiete