Verfahren und Vorrichtung zur Vermeidung von Storüngen in Chip

Details

Veröffentlichungs-Nr.

EP2849363

Aktenzeichen

EP13306263

Anmeldetag

16. September 2013

Veröffentlichung

13. Juni 2018

Erteilung

13. Juni 2018

Rechtsraum

EP

IPC

H04B15/04

Abstract

A method of rejecting spurs within a chip containing analog and digital functions, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising: - determining original analog rejection bandwidths associated with the operation of analog functions; - identifying original spurs associated with the operation of the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth based on the original analog rejection bandwidths; - obtaining final spurs based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL to shift the output frequency of said HF fractional PLL by the frequency shift.

Anmelder

Firma

ST-Ericsson SA

Land

🇨🇭 Schweiz

Fachgebiete