Verzögerungsregelschleifenschaltung und Verfahren zur Steuerung einer Phasendifferenz in einer Verzögerungsregelschleifenschaltung

Details

Veröffentlichungs-Nr.

EP2894786

Aktenzeichen

EP14151139

Anmeldetag

14. Januar 2014

Veröffentlichung

27. Februar 2019

Erteilung

27. Februar 2019

Rechtsraum

EP

IPC

H03L7/081H03L7/085

Abstract

A delay-locked loop circuit comprises a delay line (DL), designed to generate at least one output clock signal (01, 02, ..., ON) on the basis of an input clock signal (IS) and a control signal (CS). The delay-locked loop circuit further comprises a phase detector (PD), configured to perform a phase comparison between the input clock signal (IS) and one of the output clock signals (01, 02, ..., ON), and to generate a first and a second detector signal (DS1, DS2) at a first and a second detector output based on the phase comparison. The detector outputs are coupled to the first and the second amplifier input (A1, A2) of an operational transconductance amplifier (OTA). A loop filter (LF) is coupled to an amplifier output (AO) of the operational transconductance amplifier (OTA) and supplies the control signal (CS).

Anmelder

Firma

Synopsys, Inc.

Land

🇺🇸 USA

Fachgebiete