Schaltungsanordnung und Verfahren zur Takt- und Datenrückgewinnung

Details

Veröffentlichungs-Nr.

EP2988450

Aktenzeichen

EP14181449

Anmeldetag

19. August 2014

Veröffentlichung

12. Juni 2019

Erteilung

12. Juni 2019

Rechtsraum

EP

IPC

H04L7/033H03L7/10H04L7/10

Abstract

A circuit arrangement for clock and data recovery comprises a control unit (CTRL), a phase-locked loop circuit (PLL) and a sampling unit (SMPL). The control unit (CTRL) is configured to derive a first reference signal (PLSN) and a second reference signal (PLSD) from an input signal (SDIN). Furthermore, the control unit (CTRL) is configured to derive a common reference signal (FREF0) from one of the first reference signal (PLSN) and the second reference signal (PLSD), selected depending on a mode of operation of the circuit arrangement. The phase-locked loop circuit (PLL) is configured to generate an oscillator signal (SOSC) based on the common reference signal (FREF0). The sampling unit (SMPL9 is configured to extract a recovered data signal (RXD) from the input signal (SDIN).

Anmelder

Firma

ams AG

Land

🇦🇹 Österreich

Fachgebiete