Breitbandige, Hochlineare D2S-Pufferschaltung mit Niedriger Ausgangsimpedanz

Details

Veröffentlichungs-Nr.

EP3104523

Aktenzeichen

EP15191028

Anmeldetag

22. Oktober 2015

Veröffentlichung

5. Februar 2020

Erteilung

5. Februar 2020

Rechtsraum

EP

IPC

H03K19/0185H03F3/50H03F3/45H03F3/30H03F3/195

Abstract

A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Anmelder

Firmen

MediaTek Inc.
MediaTek, Inc

Land

🇹🇼 Taiwan

Fachgebiete