Verfahren zur Bestimmung eines Überlagerungsfehlers, Herstellungsverfahren und System zur Herstellung eines Mehrschichtigen Halbleiterbauelements und Dadurch Hergestelltes Halbleiterbauelement

Details

Veröffentlichungs-Nr.

EP3171396

Aktenzeichen

EP15195083

Anmeldetag

18. November 2015

Veröffentlichung

24. Mai 2017

Rechtsraum

EP

IPC

H01L21/66G03F7/20

Abstract

This document describes a method of determining an overlay error during manufacturing of a multilayer semiconductor device. Manufacturing of the semiconductor device comprises forming a stack of material layers comprising depositing of at least two subsequent patterned layers (26, 27) of semiconductor material, the patterned layers comprising a first patterned layer (26) having a first marker element (29) and a second patterned layer (27) having a second marker element (37). The determining of the overlay error comprises determining relative positions of the first and second marker element in relation to each other, such as to determine the overlay error between the first patterned layer and the second patterned layer. In addition an imaging step is performed on at least one of said first and second patterned layer, for determining relative positions of the respective first (29) or second (37) marker element and a pattern feature of a device pattern (30, 36) comprised by said respective first (26) and second (27) patterned layer.

Anmelder

Firma

Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

Land

🇳🇱 Niederlande

Fachgebiete