Pegelverschiebungsreglerschaltung

Details

Veröffentlichungs-Nr.

EP3182241

Aktenzeichen

EP15200060

Anmeldetag

15. Dezember 2015

Veröffentlichung

10. Juli 2019

Erteilung

10. Juli 2019

Rechtsraum

EP

IPC

G05F1/46

Abstract

A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (ISO) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F1, F2) may optionally be provided to improve the phase response.

Anmelder

Firma

ams AG

Land

🇦🇹 Österreich

Fachgebiete