Nichtflüchtiges Schattenloses Flip-Flop

Details

Veröffentlichungs-Nr.

EP3200192

Aktenzeichen

EP16000198

Anmeldetag

27. Januar 2016

Veröffentlichung

6. Januar 2021

Erteilung

6. Januar 2021

Rechtsraum

EP

IPC

G11C14/00

Abstract

Summarizing the invention, a memory circuit (30) is provided. The memory circuit (30) comprises a volatile memory (110); a write circuit (120); a first non-volatile memory (131) and a second non-volatile memory (132); a read circuit (140); and at least one selector circuit; wherein: the memory circuit (30) is configured to receive alternatively one of a first level clock signal and a second level clock signal; the memory circuit (30) is configured such that during each first level clock signal: the write circuit (120) is configured to write new data stored in the volatile memory (110) as current data into the first non-volatile memory (131) and the second non-volatile memory (132); and the volatile memory (110) is configured to transmit the new data as the current data to the at least one selector circuit; the memory circuit (30) is configured such that during each second level clock signal: the read circuit (140) is configured to read the current data stored in the first non-volatile memory (131) and in the second non-volatile memory (132) and transmit the current data to the at least one selector circuit; and the volatile memory (110) is configured to store new data; and the at least one selector circuit is configured to output the current data transmitted either by the volatile memory (110) or by the read circuit (140), depending on whether the memory circuit (30) is receiving the first level clock signal or the second level clock signal. Furthermore, a microprocessor comprising one or more memory circuits (30) is provided, as well as a method for storing information in the memory circuit (30).

Anmelder

Firma

Karlsruher Institut für Technologie

Land

🇩🇪 Deutschland

Fachgebiete