Leistungsbeurteilung von Hardwaredesigns mit Formaler Verifikation

Details

Veröffentlichungs-Nr.

EP3249535

Aktenzeichen

EP17172921

Anmeldetag

25. Mai 2017

Veröffentlichung

7. Oktober 2020

Erteilung

7. Oktober 2020

Rechtsraum

EP

IPC

G06F11/30G06F11/34G06F11/36G06F30/3323G06F30/39G06F119/18

Abstract

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Anmelder

Firma

Imagination Technologies Limited

Land

🇬🇧 Großbritannien

Fachgebiete