Prozessor und Steuerungsverfahren für Prozessor

Details

Veröffentlichungs-Nr.

EP3264261

Aktenzeichen

EP17172714

Anmeldetag

24. Mai 2017

Veröffentlichung

30. Dezember 2020

Erteilung

30. Dezember 2020

Rechtsraum

EP

IPC

G06F9/30G06F9/345G06F9/38

Abstract

A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Anmelder

Firma

Fujitsu Limited

Land

🇯🇵 Japan

Fachgebiete