Taktanpassung für Spannungsabfall

Details

Veröffentlichungs-Nr.

EP3270257

Aktenzeichen

EP16201253

Anmeldetag

29. November 2016

Veröffentlichung

27. Februar 2019

Erteilung

27. Februar 2019

Rechtsraum

EP

IPC

G06F1/08G06F1/30

Abstract

A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals [220, 221, 222, 223, 224, 225, 226, 227], each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.

Anmelder

Firma

Advanced Micro Devices, Inc.

Land

🇺🇸 USA

Fachgebiete