Ddr-Speicherfehlerkorrektur

Details

Veröffentlichungs-Nr.

EP3270290

Aktenzeichen

EP16203781

Anmeldetag

13. Dezember 2016

Veröffentlichung

24. März 2021

Erteilung

24. März 2021

Rechtsraum

EP

IPC

G06F11/10

Abstract

In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

Anmelder

Firma

Advanced Micro Devices, Inc.

Land

🇺🇸 USA

Fachgebiete