Priorisierte Fehlererkennung und Planung

Details

Veröffentlichungs-Nr.

EP3364416

Aktenzeichen

EP18152855

Anmeldetag

22. Januar 2018

Veröffentlichung

7. November 2018

Rechtsraum

EP

IPC

G11C29/52G06F11/10

Abstract

An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined functions. The logic circuits configured by the CRAM sectors may vary in their criticality to the operation of the integrated circuit. A prioritized error detection schedule may be provided to error detection circuitry, allowing a more frequent check of sectors that are used to configure logical circuitry that is critical to the operation of the integrated circuit. Upon detecting an error in a given CRAM sector, a sensitivity map may be used to determine the logical location corresponding to the errant CRAM sector. A sensitivity processor may assign a criticality level to the logical location, and appropriate corrective action for the errant CRAM sector may be determined based on the criticality level and the logical location corresponding to the sector.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete