Oszillatorschaltung mit Komparatorverzögerungsunterdrückung

Details

Veröffentlichungs-Nr.

EP3393040

Aktenzeichen

EP17166860

Anmeldetag

18. April 2017

Veröffentlichung

24. Oktober 2018

Rechtsraum

EP

IPC

H03K3/0231H03B5/20

Abstract

The oscillator circuit comprises first and second integrator units (100, 200) with a first capacitor (110) charged at a first integration node (121) and a second capacitor (210) charged at a second integration node (221). A comparator unit (330) is arranged between a first switching unit (310), which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit (320). The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit (400) configured to provide signals (C1, C2, D1, D2, E1, E2, F1, F2) controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Anmelder

Firmen

ams AG
AMS AG

Land

🇦🇹 Österreich

Fachgebiete