Vertikaler Asymmetrischer Zweipoliger Biristor auf Germanium Basis für Vertikale Gatelose und Kondensatorlose Dram-Zelle und Verfahren zur Herstellung davon

Details

Veröffentlichungs-Nr.

EP3428972

Aktenzeichen

EP18183260

Anmeldetag

12. Juli 2018

Veröffentlichung

11. März 2020

Erteilung

11. März 2020

Rechtsraum

EP

IPC

H01L29/861H01L27/102H01L21/329H01L29/16H01L29/165

Abstract

A vertical-type two-terminal biristor based on germanium improving memory performance and a method for manufacturing thereof are provided. When comparing with a three-terminal device, it is possible to increase integration because there is no gate and capacitor, and problems related to insulation degradation may be solved. Also, it may be operated at low voltage by using a germanium substrate, and problems related to leakage current may be solved because semiconductor layers having different doping concentrations are included. Also, it may protect semiconductor layers by depositing ACL (Amorphous Carbon Layer) on the semiconductor layers when wet etching.

Anmelder

Firma

Korea Advanced Institute of Science and Technology

Land

🇰🇷 Südkorea

Fachgebiete