Analog-Digital-Wandlerschaltung und Verfahren zur Analog-Digital-Umwandlung

Details

Veröffentlichungs-Nr.

EP3439182

Aktenzeichen

EP17183983

Anmeldetag

31. Juli 2017

Veröffentlichung

1. März 2023

Erteilung

1. März 2023

Rechtsraum

EP

IPC

H03M1/56H04N5/357H03M1/06// H03M1/12

Abstract

In an embodiment an analog-to-digital converter circuit has an input (20) for receiving at least a first analog signal level (Sin), a ramp generator (RG) adapted to provide a ramp signal (Srmp) having a constant and adjustable starting level (Vrst) which splits into a first section (P1) which is rising and a second section (P2) which is falling concurrently to the first section's (P1) rising, wherein the starting level (Vrst) lies within an input range of the analog-to-digital converter circuit, a comparison unit (CMP) which is coupled by its first input to the input (20) of the analog-to-digital converter circuit and is coupled by its second input in a switchable manner to the ramp generator (RG), a counter (CNT) which is coupled to a control unit (CTL), and the control unit (CTL) which is coupled to an output of the comparison unit (CMP), wherein the control (CTL) unit is prepared to enable the counter (CNT) depending on a comparison of the ramp signal (Srmp) with the first analog signal level (Sin) and to determine a digital value (Dv) as a function of a count (Ct) of the counter (CNT) reached at an intersection point of the ramp signal (Vramp) with at least the first analog signal level (Sin).

Anmelder

Firma

ams International AG

Land

🇨🇭 Schweiz

Fachgebiete