Sortieren von Speicheradressanforderungen für den Parallelen Speicherzugriff

Details

Veröffentlichungs-Nr.

EP3460669

Aktenzeichen

EP18194678

Anmeldetag

14. September 2018

Veröffentlichung

12. August 2020

Erteilung

12. August 2020

Rechtsraum

EP

IPC

G06F12/06G06F13/16

Abstract

An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address, the apparatus comprising: a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; a plurality of combination logic units, each combination logic unit being configured to: receive a predetermined selection of bits of the binary classification dataset; and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset; and output generating logic configured to select between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

Anmelder

Firma

Imagination Technologies Limited

Land

🇬🇧 Großbritannien

Fachgebiete