Fehlerprüfung für ein zwischen einer Ersten und einer Zweiten Taktdomäne Übertragenes Primärsignal

Details

Veröffentlichungs-Nr.

EP3573240

Aktenzeichen

EP19173514

Anmeldetag

9. Mai 2019

Veröffentlichung

25. August 2021

Erteilung

25. August 2021

Rechtsraum

EP

IPC

H03K19/003H03K19/007

Abstract

An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface (78) and a first redundant interface (80) in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface (82) and second redundant interface (84) in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry (87) is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Anmelder

Firma

ARM Limited

Land

🇬🇧 Großbritannien

Fachgebiete