Verfahren und Anordnung zur Handhabung des Speicherzugriffs für einen Tcf-Bewussten Prozessor

Details

Veröffentlichungs-Nr.

EP3671457

Aktenzeichen

EP18215559

Anmeldetag

21. Dezember 2018

Veröffentlichung

25. Juni 2025

Erteilung

25. Juni 2025

Rechtsraum

EP

IPC

G06F9/52G06F9/38

Abstract

An arrangement for handling shared data memory access for a TCF-aware processor. The arrangement comprises at least a flexible latency handling unit (601) comprising local memory (602) and related control logic, said local memory being provided for storing shared data memory access related data. The arrangement is configured to receive at least one TCF comprising at least one instruction, the at least one instruction being associated with at least one fiber, wherein the flexible latency handling unit is configured to determine if shared data memory access is required by the at least one instruction, if shared data memory access is required, send a shared data memory access request, via the flexible latency handling unit, observe, essentially continuously, if a reply to the shared data memory access request is received, suspend continued execution of the instruction until a reply is received, and continue execution of the instruction after receiving the reply so that the delay associated with the shared data memory access is dynamically determined by the actual required shared data memory access latency.

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Firmen

Flow-computing Oy
Teknologian tutkimuskeskus VTT Oy

Land

🇫🇮 Finnland

Fachgebiete