Sot-Multibit-Speicherzelle

Details

Veröffentlichungs-Nr.

EP3799049

Aktenzeichen

EP19199882

Anmeldetag

26. September 2019

Veröffentlichung

12. März 2025

Erteilung

12. März 2025

Rechtsraum

EP

IPC

G11C11/16G11C11/18G11C11/56H10N50/85

Abstract

The present disclosure provides a multibit memory cell (100), including a plurality of SOT tracks including at least a first SOT track (110) and a second SOT track (112) separate from the first SOT track, and a plurality of MTJs including at least a first MTJ (120) provided on the first SOT track, and a second MTJ (122) and a third MTJ (124) provided on the second SOT track. The cell further includes an electrically conductive path (130) connecting the first MTJ and the second MTJ together, and a plurality of terminals (140-145, of which some may be optional) for providing a first SOT write current for the first MTJ, a second SOT write current for the second MTJ, and at least one of the second SOT write current for the third MTJ, a third SOT write current for the third MTJ, and an STT write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current (160) through all the MTJs in series.

Anmelder

Firmen

IMEC VZW
Katholieke Universiteit Leuven KU Leuven Research & Development
Imec VZW

Land

🇧🇪 Belgien

Fachgebiete