Halbleitermodul und Verfahren zur Herstellung davon

Details

Veröffentlichungs-Nr.

EP3806142

Aktenzeichen

EP19201817

Anmeldetag

8. Oktober 2019

Veröffentlichung

21. Mai 2025

Erteilung

21. Mai 2025

Rechtsraum

EP

IPC

H01L23/26H01L23/053H01L23/31H01L25/07H01L23/049H01L23/00

Abstract

A power semiconductor module arrangement (100) includes a semiconductor substrate (10) arranged within a housing (7), the housing (7) comprising sidewalls, at least one semiconductor body (20) arranged on a top surface of the semiconductor substrate (10), a first protective layer (5) arranged on the top surface of the semiconductor substrate (10), thereby covering the at least one semiconductor body (20), a second protective layer (6) for protecting the power semiconductor module arrangement (100), and a seal (8). The second protective layer (6) comprises a first material and a second material (61), wherein the second material (61) is distributed within the first material and comprises a reactant, wherein the reactant is configured to chemically react with, trap, adsorb, or absorb corrosive gases. The second protective layer (6) covers at least a top surface of the first protective layer (5), wherein a top surface of the first protective layer (5) is a surface facing away from the semiconductor substrate (10). The seal (8) is arranged between the sidewalls of the housing (7) and the semiconductor substrate (10) and comprises a third material and a fourth material (62), wherein the fourth material (62) is distributed within the third material and comprises a reactant, wherein the reactant is configured to chemically react with, trap, adsorb, or absorb corrosive gases.

Anmelder

Firma

Infineon Technologies AG

Land

🇩🇪 Deutschland

Fachgebiete