Speicherleistungsverwaltungsverfahren und Prozessorsystem

Details

Veröffentlichungs-Nr.

EP3945424

Aktenzeichen

EP21175301

Anmeldetag

21. Mai 2021

Veröffentlichung

17. Januar 2024

Erteilung

17. Januar 2024

Rechtsraum

EP

IPC

G06F12/02G06F1/3234G06F1/3287

Abstract

A method of power management in a processor system is described. The processor system includes a processor coupled to a memory comprising a plurality of memory banks. The memory has a region configurable as a heap region. The processor system executes cryptographic operations. A memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation (302). A further memory bank is allocated to the heap region (304). The processor system switches to a first operating mode by setting the two memory banks to an active state (306). The processor system switches to a second operating mode by setting the first memory bank to a retention state and the further memory bank to a power-down state (308).

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA

Fachgebiete