Verzögerungsschaltung und Verzögerungsstruktur

Details

Veröffentlichungs-Nr.

EP3998705

Aktenzeichen

EP21777918

Anmeldetag

1. Juni 2021

Veröffentlichung

10. Juli 2024

Erteilung

10. Juli 2024

Rechtsraum

EP

IPC

H03K5/13H03K5/134H03K5/00

Abstract

The present disclosure provides a delay circuit and a delay structure. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal. A delay time between a rising edge of the second delay signal and the rising edge of the pulse signal is denoted as a rising edge delay time; a delay time between a falling edge of the second delay signal and the falling edge of the pulse signal is denoted as a falling edge delay time; a variation value, varying with a first parameter, of the rising edge delay time and/or the falling edge delay time is within a first range, and the first parameter includes at least one of the following: manufacturing process, power supply voltage wave, or working temperate of the delay circuit.

Anmelder

Firma

Changxin Memory Technologies, Inc.

Land

🇨🇳 China

Fachgebiete