Verfahren und Vorrichtung zur Datenübertragung in einer Hierarchischen Cache-Schaltung

Details

Veröffentlichungs-Nr.

EP4006734

Aktenzeichen

EP20386053

Anmeldetag

25. November 2020

Veröffentlichung

8. Mai 2024

Erteilung

8. Mai 2024

Rechtsraum

EP

IPC

G06F12/126

Abstract

Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

Anmelder

Firma

ARM Limited

Land

🇬🇧 Großbritannien

Fachgebiete