Logische Zelle mit Kleiner Zellenverzögerung

Details

Veröffentlichungs-Nr.

EP4027386

Aktenzeichen

EP21215515

Anmeldetag

17. Dezember 2021

Veröffentlichung

7. September 2022

Rechtsraum

EP

IPC

H01L27/02H01L21/8238// H01L27/118

Abstract

A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

Anmelder

Firma

MediaTek Inc.

Land

🇹🇼 Taiwan

Fachgebiete