Kombinieren von Kompression, Partitionierung und Quantisierung von Dl-Modellen für den Einbau in Hardware-Prozessoren

Details

Veröffentlichungs-Nr.

EP4036811

Aktenzeichen

EP21195536

Anmeldetag

8. September 2021

Veröffentlichung

6. August 2025

Erteilung

6. August 2025

Rechtsraum

EP

IPC

G06N3/063G06N3/082G06N3/088

Abstract

Small and compact Deep Learning models are required for embedded AI in several domains. In many industrial use-cases, there are requirements to transform already trained models to ensemble embedded systems or re-train those for a given deployment scenario, with limited data for transfer learning. Moreover, the hardware platforms used in embedded application include FPGAs, AI hardware accelerators, System-on-Chips and on-premises computing elements (Fog / Network Edge). These are interconnected through heterogenous bus / network with different capacities. Method of the present disclosure finds how to automatically partition a given DNN into ensemble devices, considering the effect of accuracy - latency power - tradeoff, due to intermediate compression and effect of quantization due to conversion to AI accelerator SDKs. Method of the present disclosure is an iterative approach to obtain a set of partitions by repeatedly refining the partitions and generating a cascaded model for inference and training on ensemble hardware.

Anmelder

Firma

Tata Consultancy Services Limited

Land

🇮🇳 Indien

Fachgebiete