Asymmetrische 8-Förmige Induktivität und Entsprechende Geschaltete Kondensatoranordnung

Details

Veröffentlichungs-Nr.

EP4040673

Aktenzeichen

EP21217060

Anmeldetag

22. Dezember 2021

Veröffentlichung

18. Februar 2026

Erteilung

18. Februar 2026

Rechtsraum

EP

IPC

H03B5/12

Abstract

A semiconductor device includes a substrate (100); a first terminal (A) and a second terminal (B); and a conductor (210) arranged on the substrate (100) between the first terminal (A) and the second terminal (B) to constitute an inductor (IN) shaped for forming a first loop (LI) and a second loop (L2). A first crossing (C) of the conductor (210) with itself is present between the first loop (LI) and the second loop (L2). The first loop (LI) and the second loop (L2) define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area.

Anmelder

Firma

MediaTek Inc.

Land

🇹🇼 Taiwan

Fachgebiete