Verarbeitungssystem, Zugehörige Integrierte Schaltung, Vorrichtung und Verfahren

Details

Veröffentlichungs-Nr.

EP4086763

Aktenzeichen

EP22168881

Anmeldetag

19. April 2022

Veröffentlichung

1. November 2023

Erteilung

1. November 2023

Rechtsraum

EP

IPC

G06F9/455

Abstract

A processing system (10a) is described. The processing system (10a) comprises a communication system (114a) having a given physical address range (PA) and a plurality of processing cores (102a). Each processing core (102a) has associated a first register (SECM) for storing a first virtual machine ID (VMID), which is inserted into requests (REQ) sent by the respective processing core (102a). A master circuit (M1) has associated a master interface circuit (MIF1), wherein the master interface circuit (MIF1) has associated a second register (SECM) for storing a second virtual machine ID (VMID[0]), which is inserted into requests (REQ) sent by the second circuit (M1). A slave circuit (SI) has associated a slave interface circuit (SIF2) configured to selectively forward read or write requests (REQ) addressed to a given address sub-range (PA3) from the communication system (114a) to the first circuit (S1). Specifically, the slave interface circuit (SIF2) has associated a third register (SECS) for storing a third virtual machine ID (VMID_FW[0]) associated with the given first address sub-range (PA3) and is configured to receive a request (REQ) addressed to the given address sub-range (PA3), extract from the request (REQ) a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID (VMID_FW[0]), and then either forwards or rejects the request (REQ).

Anmelder

Firmen

STMicroelectronics Application GmbH
STMicroelectronics International N.V.

Land

🇩🇪 Deutschland

Fachgebiete