Verarbeitungssystem, Zugehörige Integrierte Schaltung, Vorrichtung und Verfahren

Details

Veröffentlichungs-Nr.

EP4120083

Aktenzeichen

EP22181460

Anmeldetag

28. Juni 2022

Veröffentlichung

30. Juli 2025

Erteilung

30. Juli 2025

Rechtsraum

EP

IPC

G06F11/10G06F11/22G06F11/07

Abstract

A processing system (10a) is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit (SMb) comprising an error detection circuit (46) configured to receive data bits (DATA) and respective Error Correction Code, ECC, bits (ECC), wherein the data bits (DATA) correspond to the first, second or third data. The safety monitor circuit (SMb) calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit (120a) receives the error signal from the safety monitor circuits (SMb). In particular the safety monitor circuit (SMb) comprises a test circuit (480) configured to provide modified data bits and/or modified ECC bits to the error detection circuit (46) as a function of connectivity test control signals (CT), whereby the error detection circuit (46) asserts the error signal as a function of the connectivity test control signals (CT). The processing system (10a) comprises also a connectivity test control circuit (130) comprising control registers programmable via the microprocessor, wherein the connectivity test control signals (CT) are generated as a function of the content of the control registers.

Anmelder

Firmen

STMicroelectronics Application GmbH
STMicroelectronics International N.V.

Land

🇩🇪 Deutschland

Fachgebiete