Ansteuerungsschaltung für Phasenwechselspeicherzellen und Verfahren zur Ansteuerung von Phasenwechselspeicherzellen

Details

Veröffentlichungs-Nr.

EP4123651

Aktenzeichen

EP22181479

Anmeldetag

28. Juni 2022

Veröffentlichung

24. Juli 2024

Erteilung

24. Juli 2024

Rechtsraum

EP

IPC

G11C13/00

Abstract

A circuit comprises a plurality of memory cells (C1, ..., CN). Each memory cell in the plurality of memory cells (C1, ..., CN) includes a phase-change memory storage element (E1) coupled in series with a respective current-modulating transistor (PH1) between a supply voltage node (V<SUPPLY>) and a reference voltage node. The current-modulating transistors (PH1) are configured to receive a drive signal (DRV _GATE) at a control terminal thereof and to inject respective programming currents (I<CELL>) into the respective phase-change memory storage elements (E1) as a function of the drive signal (DRV_GATE). A driver circuit (32) is configured to produce the drive signal (DRV _GATE) at a common control node (N<C>), and the common control node (N<C>) is coupled to the control terminals of the current-modulating transistors (PH1) in the plurality of memory cells (C1, ..., CN). The drive signal (DRV _GATE) modulates the programming currents (I<CELL>) to produce set programming current pulses and reset programming current pulses. A current generator circuit (80) is configured to inject a compensation current (I<DRV_GATE>) into the common control node (N<C>) in response to the current-modulating transistors (PH1) injecting the programming currents (I<CELL>) into the respective phase-change memory storage elements (E1).

Anmelder

Firma

STMicroelectronics S.r.l.

Land

🇮🇹 Italien

Fachgebiete