Versetzte Verbindungsstruktur

Details

Veröffentlichungs-Nr.

EP4145498

Aktenzeichen

EP21195319

Anmeldetag

7. September 2021

Veröffentlichung

8. März 2023

Rechtsraum

EP

IPC

H01L21/768H01L23/528

Abstract

A method for forming an interconnection structure (100) for a semiconductor device is disclosed, comprising forming a conductive layer (110) on an insulating layer (120), etching the conductive layer to form a first set of conductive lines (101), forming a first set of spacer lines (130) on sidewalls of the first set of conductive lines, and forming a second set of conductive lines (102) in trenches (140) defined by the first set of spacer lines, wherein a bottom (142) of the trenches is recessed into the insulating layer, or formed by a spacer material (150) arranged on the insulating layer, such that a bottom portion of the first set of conductive lines and a bottom portion of the second set of conductive lines are arranged on different vertical levels (H1, H2).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete