Verfahren zur Herstellung einer Verbindungsstruktur

Details

Veröffentlichungs-Nr.

EP4167275

Aktenzeichen

EP21203176

Anmeldetag

18. Oktober 2021

Veröffentlichung

19. April 2023

Rechtsraum

EP

IPC

H01L21/768H01L23/528H01L23/535H10D84/01H10D84/03// H10D88/00

Abstract

A method for forming an interconnection structure for a first transistor and a second transistor is provided, wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second (122) channel portion, and wherein the channel portions are stacked above each other on a substrate. The method comprises forming a conductive line (130) extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure (132) for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further comprises forming a via hole (146) exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure (142), and forming a conductive structure (140) on the second vertical interconnect structure.

Anmelder

Firmen

IMEC VZW
Imec VZW

Land

🇧🇪 Belgien

Fachgebiete