Taktrückgewinnungsschaltung, Entsprechende Vorrichtung und Verfahren

Details

Veröffentlichungs-Nr.

EP4175215

Aktenzeichen

EP22201648

Anmeldetag

14. Oktober 2022

Veröffentlichung

24. April 2024

Erteilung

24. April 2024

Rechtsraum

EP

IPC

H04L7/033H03K5/12H03L7/08

Abstract

A clock recovery circuit (10) comprises an input node (IN) configured to receive a data signal (Data_in) having a data rate and a digital oscillator (22, 24) such as a Delay Lock Loop to produce a local clock signal (CLK) with a frequency higher than the data rate of the data signal (Data_in). A counter (260) clocked by the local clock signal (CLK) is configured to have its count value sampled and then reset at the rising and falling edges of the data signal (Data_in) and a storage block (266) coupled to the counter (260) is configured to store a count value that is is updated (SE) in response to the current sampled count value of the counter (260) lying in an update range between a lower bound (e.g., half the value previously stored minus a count margin) and an upper bound (e.g., the value previously stored plus a count margin). A threshold value set (Edge1, Edge2) is produced as a function of the updated count value stored in the storage block (266). Sampling circuitry (14) configured to receive the data signal (Data_in) at the input node (IN) samples (SI) the data signal (Data_in) at the input node and provide at an output node (OUT) a sampled version (Sampled Data_in) of the data signal (Data_in) at the input node (IN) in response to the count value of the counter (260) reaching any of the threshold values in the threshold value set (Edge1, Edge 2).

Anmelder

Firma

STMicroelectronics S.r.l.

Land

🇮🇹 Italien

Fachgebiete