Speicherkonfiguration in einem Datenverarbeitungssystem

Details

Veröffentlichungs-Nr.

EP4250093

Aktenzeichen

EP23163108

Anmeldetag

21. März 2023

Veröffentlichung

7. Mai 2025

Erteilung

7. Mai 2025

Rechtsraum

EP

IPC

G06F8/65G06F11/14

Abstract

A System on Chip (SoC) includes a first core coupled to an interconnect; a second core coupled to the interconnect; a memory coupled to the interconnect and including a plurality of evenly sized partitions; and storage circuitry configured to store memory configuration information. The memory configuration information defines a memory configuration and is configured to indicate a series of swappable segments for each core of the SoC by indicating, for each core, a first number of partitions of the memory assigned to each of a first swappable segment and a second swappable segment for the core, the first swappable segment designated as an active segment and the second swappable segment designated as a first backup segment, and an enable indicator to indicate whether or not to assign the first number of partitions to a third swappable segment designated as a second backup segment.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA

Fachgebiete