Halbleitergehäuse mit einem Dicken Logischen Chip

Details

Veröffentlichungs-Nr.

EP4297077

Aktenzeichen

EP23179675

Anmeldetag

16. Juni 2023

Veröffentlichung

1. Mai 2024

Rechtsraum

EP

IPC

H01L23/16H01L23/00H01L25/065H01L25/18H01L25/03H01L23/538// H01L25/10H01L23/485H01L23/488H01L23/49H01L23/48H01L21/60H01L23/498

Abstract

A semiconductor package (2) includes a bottom substrate (100) and a top substrate (300) space apart from the bottom substrate (100) such that the bottom substrate (100) and the top substrate (300) define a gap therebetween. A logic die (50) and a memory die (70) are mounted on a top surface (100a) of the bottom substrate (100) in a side-by-side fashion. The logic die (50) may have a thickness not less than 125 micrometers. A connection structure (90) is disposed between the bottom substrate (100) and the top substrate (300) around the logic die (50) and the memory die (70) to electrically connect the bottom substrate (100) with the top substrate (300). A sealing resin (SM) fills in the gap between the bottom substrate (100) and the top substrate (300) and sealing the logic die (50), the memory die (70), and the connection structure (90) in the gap.

Anmelder

Firma

MediaTek Inc.

Land

🇹🇼 Taiwan

Fachgebiete