Verschachtelungsschaltung und Kommunikationsgerät

Details

Veröffentlichungs-Nr.

EP4325726

Aktenzeichen

EP23158513

Anmeldetag

24. Februar 2023

Veröffentlichung

17. September 2025

Erteilung

17. September 2025

Rechtsraum

EP

IPC

H03M13/27H03M13/00

Abstract

According to an arrangement, an interleave circuit includes a reordering circuit (110) and an address calculation circuit (120). The reordering circuit (110) is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit (120) is configured to calculate write addresses for writing the n-pieces of output data into a first storage device (130a, 130b) and read addresses for reading out the n-pieces of output data from the first storage device (130a, 130b).

Anmelder

Firma

KABUSHIKI KAISHA TOSHIBA

Land

🇯🇵 Japan

Fachgebiete