Durchgangsanpassung in Integrierten Schaltungen auf der Basis von Maschinenlernen

Details

Veröffentlichungs-Nr.

EP4394646

Aktenzeichen

EP23200721

Anmeldetag

29. September 2023

Veröffentlichung

3. Juli 2024

Rechtsraum

EP

IPC

G06F30/27G06F30/3953G06F30/398G03F1/36// G06F119/22G06F119/18

Abstract

Methods, apparatus, systems, and articles of manufacture (402) are disclosed to adjust vias (506, 508, 514) in integrated circuits, ICs, based on machine learning, ML. An example apparatus computes a dimension by which to extend a via based on at least one of a first metal wire in a first layer of the IC above the via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the IC below the via (520). The example apparatus also computes a shifted position of the via (508) based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the via, the width and the position predicted by an ML model. Additionally, the example apparatus adjusts a configuration file (510) corresponding to the IC based on at least one of the dimension or the shifted position of the via.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete