Speicherverarbeitungssystem mit Erhöhter Effizienz und Verfahren dafür

Details

Veröffentlichungs-Nr.

EP4418128

Aktenzeichen

EP23195935

Anmeldetag

7. September 2023

Veröffentlichung

3. September 2025

Erteilung

3. September 2025

Rechtsraum

EP

IPC

G06F12/1009G06F12/1027

Abstract

A memory processing system (100) includes a processor (10), a main memory (20), and a MMU (30) coupled to the processor (10) and the main memory (20) . The processor (10) is used to generate a plurality of virtual addresses. The main memory (20) includes a plurality of data corresponding to physical addresses in a main page table (22) . The main page table (22) is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit (30) includes a TLB (32) coupled to the processor (10) and the main memory (20), a table walk unit (34) coupled to the TLB (32) and the main memory (20), and a merger (36) coupled to the TLB (32) and the processor (10). The TLB (32) performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB (32) or a second page table in the table walk unit (34) or the main page table (22) in the main memory (20) .

Anmelder

Firma

MediaTek Inc.

Land

🇹🇼 Taiwan

Fachgebiete