Integrierte Schaltung mit einer Prüfschaltung, Zugehöriges Verfahren und Computerprogrammprodukt

Details

Veröffentlichungs-Nr.

EP4425196

Aktenzeichen

EP24157104

Anmeldetag

12. Februar 2024

Veröffentlichung

4. September 2024

Rechtsraum

EP

IPC

G01R31/3185

Abstract

An integrated circuit is disclosed. The integrated circuit comprises a sequential logic circuit (20) and a circuit (204, 220) configured to change operation as a function of a subset of the state output signals (Q) provided by state flip-flops (202; 402) of the sequential logic circuit (20). A test circuit (300, 404, 406) is configured to determine whether a test mode signal (SCAN_MODE) is asserted and, when the test mode signal (SCAN_MODE) is asserted, write and read (TE, TI, TO) the content of the state flip-flops (202; 402) in order to test the operation of the sequential logic circuit (20).In particular, the processing system (10) comprises also at least one storage circuit (408). Each storage circuit (408) is interposed between the circuit (204, 220) and a respective state output signal (Q), wherein each storage circuit (408) is configured to receive the respective state output signal (Q) and provide a modified state signal (Q') to the circuit (204, 220). Specifically, when the test mode signal (SCAN_MODE) is de-asserted, the storage circuit (408) provides the received state output signal (Q) in a transparent manner to the circuit (204, 220) and stores the received state output signal (Q) to a storage element (4082; 4086). Conversely, when the test mode signal (SCAN_MODE) is asserted, the storage circuit (408) provides the stored state output signal (Q') to the circuit (204, 220).

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete