Leseverstärkerschaltung, Zugehörige Speichervorrichtung und Betriebsverfahren

Details

Veröffentlichungs-Nr.

EP4471773

Aktenzeichen

EP24167364

Anmeldetag

28. März 2024

Veröffentlichung

10. Dezember 2025

Erteilung

10. Dezember 2025

Rechtsraum

EP

IPC

G11C7/06G11C13/00

Abstract

A sense amplifier circuit (52) for a memory device (10) includes a first input terminal (304_L) and a second input terminal (304_R) configured for coupling (SW_YMPS,L, SW_YMPS,R) to a first memory sensing node (302_L) and a second memory sensing node (302_R), respectively. A sensing circuit (30') is coupled to the first (304_L) and second (304_R) input terminals and is configured to sense a differential signal therebetween. A first boosting capacitor (C_BSTL) has a first terminal coupled to the first input terminal (304_L) and a second terminal coupled to a floating node (62). A second boosting capacitor (C_BSTR) has a first terminal coupled to the second input terminal (304_R) and a second terminal coupled to the floating node (62). A control circuitry (64, SL, SR) is configured to receive a bit line boosting activation signal (YMPS_PRECH_BST). In response to the bit line boosting activation signal (YMPS_PRECH_BST) having a first value, the first terminals of the first (C_BSTL) and second (C_BSTR) boosting capacitors are coupled to a regulated supply node (108) that provides a regulated supply voltage (V_REG) and the floating node (62) is driven to a ground voltage. In response to the bit line boosting activation signal (YMPS_PRECH_BST) having a second value, the first terminals of the first (C_BSTL) and second (C_BSTR) boosting capacitors are decoupled from the regulated supply node (108) and the floating node (62) is driven to the regulated supply voltage (V_REG).

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete