Taktbereichsüberquerungssynchronisationsschaltungen und Verfahren zur Gewährleistung einer Ordnungsgemässen Datensignalreihenfolge

Details

Veröffentlichungs-Nr.

EP4498204

Aktenzeichen

EP24188539

Anmeldetag

15. Juli 2024

Veröffentlichung

18. Juni 2025

Erteilung

18. Juni 2025

Rechtsraum

EP

IPC

G06F1/04G06F1/12G06F13/42

Abstract

Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete