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Details

Veröffentlichungs-Nr.

EP4498432

Aktenzeichen

EP24190138

Anmeldetag

22. Juli 2024

Veröffentlichung

23. April 2025

Rechtsraum

EP

IPC

H01L25/075H01L25/16H10H20/857H10H29/39

Abstract

A pixel circuit layer (PCL) of a display device is on a base layer (BSL) and includes conductive patterns configuring at least one of a transistor, a capacitor, or a signal line. A first electrode (ELT1) and a second electrode (ELT2) are on the pixel circuit layer (PCL) and are spaced from each other. A bank (not shown in figure 10) is on the first electrode (ELT1) and the second electrode (ELT2) and includes an opening. Light emitting elements (LD) are between the first electrode (ELT1) and the second electrode (ELT2) in the opening of the bank. In the opening of the bank, a space between the first electrode (ELT1) and the second electrode (ELT2) that are spaced from each other by a distance corresponding to a length of the light emitting elements (LD) is defined as a lane (EA) in which the light emitting elements (LD) are located. In a plan view, the lane (EA) does not overlap conductive patterns of the pixel circuit layer (PCL), and is spaced from said patterns by half of the length of the light emitting elements (LD).

Anmelder

Firma

Samsung Display Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete