Nichtflüchtige Speichervorrichtung, Zugehöriges Verfahren und System

Details

Veröffentlichungs-Nr.

EP4513486

Aktenzeichen

EP24192638

Anmeldetag

2. August 2024

Veröffentlichung

26. Februar 2025

Rechtsraum

EP

IPC

G11C5/02G11C7/18G11C13/00

Abstract

A device (20), comprising a memory array (28) comprising memory cells arranged in a set of memory portions (280, 282) and addressable via a pair of row and column values, wherein each memory portion in the set of memory portions (280, 282) comprises at least one sector of memory cells (S) arranged in rows and columns. The device (20) comprises: a set of sense amplifier circuits (240) coupled to and interposed adjacent memory portions in the set of memory portions (280, 282) of the memory array (28); a control circuit (CL) configured to provide at least one address signal (AS) indicative of a pair of row and column values to localize at least one addressed memory cell in the memory array (28), the control circuit (CL) being further configured to issue read or write access requests towards the at least one addressed memory cell in the memory array (28); a first set of access devices (YO) configured to be made conductive to couple (LBL) an addressed memory cell in a respective memory portion of the set of memory portions (280, 282) of the memory array (28) to the respective sense amplifier circuit in the set of sense amplifier circuits (240) in response to a read access request issued by the control circuit (CL); a second set of access devices (11) configured to be made conductive to couple an addressed memory cell in a respective memory portion of the set of memory portions (280, 282) of the memory array (28) to the programming bitline (WL) in response to a write access request issued by the control circuit (CL).

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete