Flächeneffiziente Vollständig Verarmte Halbleiter-Auf-Isolator-Struktur mit Transistoren mit Gemischter Schwellenspannung

Details

Veröffentlichungs-Nr.

EP4535414

Aktenzeichen

EP24168619

Anmeldetag

5. April 2024

Veröffentlichung

9. April 2025

Rechtsraum

EP

IPC

H10D84/85H10D86/01H10D86/00

Abstract

Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

Anmelder

Firma

GlobalFoundries U.S. Inc.

Land

🇺🇸 USA

Fachgebiete