Grabenkondensator in einer Verbindungsregion

Details

Veröffentlichungs-Nr.

EP4580331

Aktenzeichen

EP24210791

Anmeldetag

5. November 2024

Veröffentlichung

2. Juli 2025

Rechtsraum

EP

IPC

H10D1/00H01L23/522H10D1/68H10D84/80

Abstract

Techniques are provided herein for forming one or more MIM trench capacitors in the interconnect region above the device layer of an integrated circuit. In an example, the MIM trench capacitor(s) are formed within one of the upper interconnect layers of the interconnect region, and thus can have a relatively high height (e.g., greater than about 200 nm). An interconnect layer included in a stack of interconnect layers includes a MIM capacitor having a first electrode (206), a capacitor dielectric (210) on the first electrode, and a second electrode (212) on the capacitor dielectric. The MIM capacitor runs along the outside surface of a plurality of dielectric fins (204), which greatly increases the surface area of the capacitor within a relatively small plan footprint. The first and second electrodes may connect with one or more topside contacts (216, 218) and/or one or more buried conductive lines (220, 222).

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete