Physikalisch Bewusste Leistungsprofiloptimierung Während eines Speichertests
Anmelder: NXP USA, Inc. 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4648052
- Aktenzeichen
- EP25173859
- Anmeldetag
- 1. Mai 2025
- Veröffentlichung
- 12. November 2025
- Rechtsraum
- EP
- IPC
- G11C5/14G11C29/08G11C29/10G11C29/26
Abstract
A method for physical-aware power profile optimization during memory test includes creating a plurality of scheduling buckets, wherein each scheduling bucket includes one or more sequentially executed test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence including a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to a test time budget. A power profile is optimized by determining a respective optimized start time of at least one test sequence from at least a physical distance between two groups of memories controlled by respective BIST controllers. The respective optimized start time is assigned to the at least one test sequence.
Anmelder
- Firma
- NXP USA, Inc.
- Land
- 🇺🇸 USA
US-amerikanische Gesellschaft des Halbleiterkonzerns NXP, die Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation und Industrieelektronik entwickelt.
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